IEEE - Institute of Electrical and Electronics Engineers, Inc. - Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

Author(s): Frederick T. Chen ; Yu-Sheng Chen ; Tai-Yuan Wu ; Tzu-Kun Ku
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 2014
Volume: 35
Page Count: 3
Page(s): 223 - 225
ISSN (Paper): 0741-3106
ISSN (Online): 1558-0563
DOI: 10.1109/LED.2013.2294809
Regular:

A 3-D resistive random access memory potentially offers lowest cost per bit and highest bit density memory architecture without the use of transistors in the array. However, without the use of... View More

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