IEEE - Institute of Electrical and Electronics Engineers, Inc. - On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes

Author(s): Chia-Yi Lin ; Hsiu-Chuan Lin ; Hung-Ming Chen
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2010
Volume: 18
Page Count: 5
Page(s): 1,220 - 1,224
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/TVLSI.2009.2021061
Regular:

In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test... View More

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