IEEE - Institute of Electrical and Electronics Engineers, Inc. - 3-D Topologies for Networks-on-Chip

Author(s): V.F. Pavlidis ; E.G. Friedman
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2007
Volume: 15
Page Count: 10
Page(s): 1,081 - 1,090
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/TVLSI.2007.893649
Regular:

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical... View More

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