IEEE - Institute of Electrical and Electronics Engineers, Inc. - Some conditions under which hierarchical verification is O(N)

Author(s): L.K. Scheffer
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2003
Volume: 22
Page Count: 4
Page(s): 643 - 646
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/TCAD.2003.810740
Regular:

Before manufacturing, each chip design must be inspected for possible errors. For example, design rule checking is used to check for adherence to the physical manufacturing rules, and static... View More

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