IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Author(s): Florian Huemer ; Thomas Polzer ; Andreas Steininger
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2018
Conference Location: Budapest, Hungary, Hungary
Conference Date: 25 April 2018
Page(s): 141 - 146
ISBN (Electronic): 978-1-5386-5754-6
ISSN (Electronic): 2473-2117
DOI: 10.1109/DDECS.2018.00032
Regular:

In view of the increasing number of clock domains found in modern ASICs, the precise characterization of metastability at their boundaries becomes crucial. In some cases, the conventional approach... View More

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