IEEE Computer Society - Testable Design of Reversible Circuits Using Parity Preserving Gates

Author(s): Hari Mohan Gaur ; Ashutosh Kumar Singh ; Umesh Ghanekar
Publisher: IEEE Computer Society
Publication Date: 1 August 2018
Volume: 35
Page(s): 56 - 64
ISSN (Electronic): 2168-2364
ISSN (Paper): 2168-2356
DOI: 10.1109/MDAT.2017.2771202
Regular:

This paper proposes an efficient design for testability technique for reversible logic circuits, which promises ultralow energy computation. -Shreyas Sen, Purdue University

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