IEEE - Institute of Electrical and Electronics Engineers, Inc. - Simultaneous voltage scaling and gate sizing for low-power design

Author(s): Chunhong Chen ; M. Sarrafzadeh
Sponsor(s): IEEE Circuits & Syst. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2002
Volume: 49
Page Count: 9
Page(s): 400 - 408
ISSN (Paper): 1057-7130
DOI: 10.1109/TCSII.2002.802964
Regular:

This paper presents a new approach using simultaneous voltage-scaling and gate-sizing for low power without violating the timing constraints. We provide the problem formulation in this... View More

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