IEEE - Institute of Electrical and Electronics Engineers, Inc. - On automatic-verification pattern generation for SoC with port-order fault model

Author(s): Chun-Yao Wang ; Shing-Wu Tung ; Jing-Yang Jou
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2002
Volume: 21
Page Count: 14
Page(s): 466 - 479
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/43.992770
Regular:

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To... View More

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