IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

Author(s): R. Venkatesan ; J.A. Davis ; K.A. Bowman ; J.D. Meindl
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2001
Volume: 9
Page Count: 14
Page(s): 899 - 912
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.974903
Regular:

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle... View More

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