IEEE - Institute of Electrical and Electronics Engineers, Inc. - Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

Author(s): I. Pomeranz ; S.M. Reddy
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2001
Volume: 9
Page Count: 11
Page(s): 679 - 689
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.953501
Regular:

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on... View More

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