IEEE - Institute of Electrical and Electronics Engineers, Inc. - Rework techniques process evaluation for chip scale packages

Author(s): T.A. Nguty ; J.D. Philpott ; N.N. Ekere ; S. Teckle ; B. Salam ; D. Rajkumar
Sponsor(s): IEEE Components, Packaging, and Manufacturing Technology Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2000
Volume: 23
Page Count: 8
Page(s): 200 - 207
ISSN (Paper): 1521-334X
ISSN (Online): 1558-0822
DOI: 10.1109/6104.873248
Regular:

The packaging formats, chip scale package (CSP) and ball grid array (BGA) have allowed significant reductions in component size compared to conventional surface mount devices (SMD) such as quad... View More

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