IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multilevel hypergraph partitioning: applications in VLSI domain

Author(s): G. Karypis ; R. Aggarwal ; V. Kumar ; S. Shekhar
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 1999
Volume: 7
Page Count: 11
Page(s): 69 - 79
ISSN (Paper): 1063-8210
ISSN (Online): 1557-9999
DOI: 10.1109/92.748202
Regular:

In this paper, we present a new hypergraph-partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergraphs is... View More

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