IEEE Computer Society - Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Author(s): Kai-Li Wang ; Bing-Yang Lin ; Cheng-Wen Wu ; Mincent Lee ; Hao Chen ; Hung-Chih Lin ; Ching-Nen Peng ; Min-Jer Wang
Publisher: IEEE Computer Society
Publication Date: 1 June 2017
Volume: 34
Page(s): 50 - 58
ISSN (Paper): 2168-2356
ISSN (Online): 2168-2364
DOI: 10.1109/MDAT.2016.2562060
Regular:

Editor's note: To reduce the manufacturing cost of heterogeneous 3-D integration, the Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the emerging packaging... View More

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