IEEE - Institute of Electrical and Electronics Engineers, Inc. - Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects

Author(s): S. Afonso ; L.W. Schaper ; J.P. Parkerson ; W.D. Brown ; S. Ang ; H.A. Naseem
Sponsor(s): IEEE Components, Packaging, and Manufacturing Technology Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 1999
Volume: 22
Page Count: 12
Page(s): 309 - 320
ISSN (Paper): 1521-3323
ISSN (Online): 1557-9980
DOI: 10.1109/6040.784478
Regular:

Scaling down on-chip interconnect cross-sectional dimensions results not only in higher circuit wiring density, but also in the long lossy line problem, wherein the long lines become highly... View More

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