IEEE - Institute of Electrical and Electronics Engineers, Inc. - A modeling technique for CMOS gates

Author(s): A. Chatzigeorgiou ; S. Nikolaidis ; I. Tsoukalas
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 1999
Volume: 18
Page Count: 19
Page(s): 557 - 575
ISSN (Paper): 0278-0070
ISSN (Online): 1937-4151
DOI: 10.1109/43.759070
Regular:

In this paper, a modeling technique for CMOS gates, based on the reduction of each gate to an equivalent inverter, is presented. The proposed method can be incorporated in existing timing... View More

Advertisement