IEEE - Institute of Electrical and Electronics Engineers, Inc. - Self-aligned gate and source drain contacts in inverted-staggered a-Si:H thin-film transistors fabricated using selective area silicon PECVD

Author(s): C.S. Yang ; W.W. Read ; C. Arthur ; A.E. Srinivasan ; G.N. Parsons
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 1998
Volume: 19
Page Count: 3
Page(s): 180 - 182
ISSN (Paper): 0741-3106
ISSN (Online): 1558-0563
DOI: 10.1109/55.678536
Regular:

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon... View More

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