IEEE - Institute of Electrical and Electronics Engineers, Inc. - 64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency

Author(s): R. Heald ; K. Shin ; V. Reddy ; I-Feng Kao ; M. Khan ; W.L. Lynch ; G. Lauterbach ; J. Petolino
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 1998
Volume: 33
Page Count: 8
Page(s): 1,682 - 1,689
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/4.726558
Regular:

Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way set-associative cache. This address adder avoids time-consuming carry propagation by... View More

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