IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits

Author(s): G.A. Ruiz
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 1998
Volume: 33
Page Count: 10
Page(s): 604 - 613
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/4.663566
Regular:

The efficient implementation of adders in differential logic can be carried out using a new generate signal (N) presented in this paper. This signal enables iterative shared transistor structures... View More

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