IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 4.1-ns compact 54/spl times/54-b multiplier utilizing sign-select Booth encoders

Author(s): G. Goto ; A. Inoue ; R. Ohe ; S. Kashiwakura ; S. Mitarai ; T. Tsuru ; T. Izawa
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 1997
Volume: 32
Page Count: 7
Page(s): 1,676 - 1,682
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/4.641687
Regular:

A 54/spl times/54-b multiplier with only 60 K transistors has been fabricated by 0.25-/spl mu/m CMOS technology. To reduce the total transistor count, we have developed two new approaches:... View More

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