IEEE - Institute of Electrical and Electronics Engineers, Inc. - Will physical scalability sabotage performance gains?

Author(s): D. Matzke
Sponsor(s): IEEE Computer Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 1997
Volume: 30
Page Count: 3
Page(s): 37 - 39
ISSN (Paper): 0018-9162
DOI: 10.1109/2.612245
Regular:

The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will... View More

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