IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 12-Bit 96Msample/s double-data-rate (DDR) pipeline ADC with speed and noise optimization for CMOS image sensors

2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE)

Author(s): Sheng Zhang ; Lin Xiaokang ; Guanjing Ren ; Shao Pengzhi
Sponsor(s): IEEE Sapporo Sect.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2014
Conference Location: Sapporo, Japan
Conference Date: 26 April 2014
Volume: 3
Page(s): 1,798 - 1,803
ISBN (CD): 978-1-4799-3195-8
ISBN (Electronic): 978-1-4799-3197-2
ISBN (Paper): 978-1-4799-3196-5
DOI: 10.1109/InfoSEEE.2014.6946232
Regular:

In this paper, a 12-bit pipeline ADC with double-data-rate topology is proposed for high-speed CMOS image sensors (CIS). With a unique ping-pang architecture and a pseudo-noise cancellation scheme... View More

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