IEEE - Institute of Electrical and Electronics Engineers, Inc. - Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in 90nm CMOS process

2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE)

Author(s): Wei-Bin Yang ; Yu-Yao Lin ; Yu-Lung Lo
Sponsor(s): IEEE Sapporo Sect.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2014
Conference Location: Sapporo, Japan
Conference Date: 26 April 2014
Volume: 3
Page(s): 1,653 - 1,656
ISBN (CD): 978-1-4799-3195-8
ISBN (Electronic): 978-1-4799-3197-2
ISBN (Paper): 978-1-4799-3196-5
DOI: 10.1109/InfoSEEE.2014.6946202
Regular:

In this paper, we analyze the circuit characteristic of static CMOS logics and provide the size ratio of PMOS to NMOS transistors under process, voltage and temperature (PVT) variations in 90nm... View More

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