IEEE - Institute of Electrical and Electronics Engineers, Inc. - Verilog-A compact model for oxide-based resistive random access memory (RRAM)

2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Author(s): Zizhen Jiang ; Shimeng Yu ; Yi Wu ; Jesse H. Engel ; Ximeng Guan ; H.-S Philip Wong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2014
Conference Location: Yokohama, Japan
Conference Date: 9 September 2014
Page(s): 41 - 44
ISBN (CD): 978-1-4799-5285-4
ISBN (Electronic): 978-1-4799-5288-5
ISBN (DVD): 978-1-4799-5286-1
ISBN (Paper): 978-1-4799-5287-8
ISSN (Paper): 1946-1569
DOI: 10.1109/SISPAD.2014.6931558
Regular:

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This... View More

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