IEEE - Institute of Electrical and Electronics Engineers, Inc. - FPGA implementation of secure image compression with 2D-DCT using Verilog HDL

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

Author(s): B. Jeevan ; C. Nagesh Bhatt ; C. V. Krishna ; K. Sivani
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2014
Conference Location: Combiatore, India
Conference Date: 6 March 2014
Page(s): 1 - 4
ISBN (Electronic): 978-1-4799-1356-5
ISBN (DVD): 978-1-4799-1355-8
DOI: 10.1109/ICDCSyst.2014.6926210
Regular:

The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog... View More

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