IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low hardware overhead implementation of 3-weight pattern generation technique for VLSI testing

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

Author(s): D. Gracia Nirmala Rani ; M. G. Mangala Meenakshi ; S. Amalin Marina
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2014
Conference Location: Combiatore, India
Conference Date: 6 March 2014
Page(s): 1 - 5
ISBN (Electronic): 978-1-4799-1356-5
ISBN (DVD): 978-1-4799-1355-8
DOI: 10.1109/ICDCSyst.2014.6926180
Regular:

Pseudorandom Built-In Self-Test (BIST) generators have been most frequently used to test the integrated circuits and systems. This scheme requires more test patterns and consumes more testing time... View More

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