IEEE - Institute of Electrical and Electronics Engineers, Inc. - An optimized SOI g-TFET and its application in a half adder circuit

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

Author(s): B. Bhowmick ; S. Baishya ; R. Goswami ; B. Dasv ; C. Joishy
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2014
Conference Location: Combiatore, India
Conference Date: 6 March 2014
Page(s): 1 - 5
ISBN (Electronic): 978-1-4799-1356-5
ISBN (DVD): 978-1-4799-1355-8
DOI: 10.1109/ICDCSyst.2014.6926156
Regular:

In this paper, gate induced band-to-band tunneling transistors are explored as a low voltage alternative because of their potential to achieve lower than 60mV/decade turn-off. Since BTBT is... View More

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