IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.75-V four-quadrant current multiplier using floating gate-MOS transistors

2014 International Electrical Engineering Congress (iEECON)

Author(s): Montree Kumngern ; Jirasak Chanwutitum
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2014
Conference Location: Chonburi, Thailand
Conference Date: 19 March 2014
Page(s): 1 - 4
ISBN (Electronic): 978-1-4799-3174-3
DOI: 10.1109/iEECON.2014.6925870
Regular:

This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed... View More

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