IEEE - Institute of Electrical and Electronics Engineers, Inc. - Probabilistic power analysis technique for low power VLSI circuits

2013 IEEE 8th International Conference on Industrial and Information Systems (ICIIS 2013)

Author(s): Vinod Kumar Joshi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2013
Conference Location: Peradeniya, Sri Lanka
Conference Date: 17 December 2013
Page(s): 616 - 621
ISBN (CD): 978-1-4799-0909-4
ISBN (Electronic): 978-1-4799-0910-0
ISBN (Paper): 978-1-4799-0908-7
DOI: 10.1109/ICIInfS.2013.6732055
Regular:

Here the author reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an... View More

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