IEEE - Institute of Electrical and Electronics Engineers, Inc. - Data — Clock setup and hold times margins correction method in high speed serial links

Ninth International Conference on Computer Science and Information Technologies (CSIT)

Author(s): Vazgen Sh Melikyan ; Arthur S. Sahakyan ; Aram H. Shishmanyan ; Nazeli V. Melikyan ; Grigor Y. Zargaryan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Yerevan, Armenia
Conference Date: 23 September 2013
Page(s): 1 - 5
ISBN (Electronic): 978-1-4799-2461-5
ISBN (Paper): 978-1-4799-2460-8
DOI: 10.1109/CSITechnol.2013.6710331
Regular:

A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time... View More

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