IEEE - Institute of Electrical and Electronics Engineers, Inc. - Chip design of 10 GHz low phase noise and small chip area PLL

2013 8th International Conference on Communications and Networking in China (CHINACOM)

Author(s): J. F. Huang ; W. C. Lai ; J. Y. Wen ; C. C. Mao
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2013
Conference Location: Guilin, China
Conference Date: 14 August 2013
Page(s): 276 - 280
ISBN (Electronic): 978-1-4799-1406-7
DOI: 10.1109/ChinaCom.2013.6694605
Regular:

This design describes one of the lowest phase noise an integer-N phase-locked loop (PLL) below 10 GHz offset region using and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a... View More

Advertisement