IEEE - Institute of Electrical and Electronics Engineers, Inc. - A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): H. Koike ; T. Ohsawa ; S. Ikeda ; T. Hanyu ; H. Ohno ; T. Endoh ; N. Sakimura ; R. Nebashi ; Y. Tsuji ; A. Morioka ; S. Miura ; H. Honjo ; T. Sugibayashi
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2013
Conference Location: Singapore, Singapore
Conference Date: 11 November 2013
Page(s): 317 - 320
ISBN (Electronic): 978-1-4799-0280-4
ISBN (Paper): 978-1-4799-0277-4
DOI: 10.1109/ASSCC.2013.6691046
Regular:

We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU... View More

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