IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Ba-Ro-Saim Sung ; Chang-Kyo Lee ; Wan Kim ; Jong-In Kim ; Hyeok-Ki Hong ; Ghil-Geun Oh ; Choong-Hoon Lee ; Michael Choi ; Ho-Jin Park ; Seung-Tak Ryu
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2013
Conference Location: Singapore, Singapore
Conference Date: 11 November 2013
Page(s): 281 - 284
ISBN (Electronic): 978-1-4799-0280-4
ISBN (Paper): 978-1-4799-0277-4
DOI: 10.1109/ASSCC.2013.6691037
Regular:

A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a low-resolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every... View More

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