IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Gautam R. Gangasani ; John F. Bulzacchelli ; Troy Beukema ; Chun-Ming Hsu ; William Kelly ; Hui H. Xu ; David Freitas ; Andrea Prati ; Daniele Gardellini ; Giovanni Cervelli ; Juergen Hertle ; Matthew Baecher ; Jon Garlett ; Robert Reutemann ; David Hanson ; Daniel W. Storaska ; Mounir Meghelli
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2013
Conference Location: Singapore, Singapore
Conference Date: 11 November 2013
Page(s): 213 - 216
ISBN (Electronic): 978-1-4799-0280-4
ISBN (Paper): 978-1-4799-0277-4
DOI: 10.1109/ASSCC.2013.6691020
Regular:

This paper describes key design features of a 32-Gb/s 4-tap FFE/15-tap DFE transceiver in 32-nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver... View More

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