IEEE - Institute of Electrical and Electronics Engineers, Inc. - 750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Alireza Rabbani Abolfazli ; Yousef R. Shayan ; Glenn E. R. Cowan
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2013
Conference Location: Singapore, Singapore
Conference Date: 11 November 2013
Page(s): 181 - 184
ISBN (Electronic): 978-1-4799-0280-4
ISBN (Paper): 978-1-4799-0277-4
DOI: 10.1109/ASSCC.2013.6691012
Regular:

Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes... View More

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