IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Venkatram Krishnaswamy ; Jinuk Luke Shin ; Sebastian Turullols ; Jason M. Hart ; Georgios Konstadinidis ; Dawei Huang
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2013
Conference Location: Singapore, Singapore
Conference Date: 11 November 2013
Page(s): 17 - 20
ISBN (Electronic): 978-1-4799-0280-4
ISBN (Paper): 978-1-4799-0277-4
DOI: 10.1109/ASSCC.2013.6690971
Regular:

The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the... View More

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