IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of a GALS-NoC Using Soft-cores on FPGAs

2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip (MCSoC)

Author(s): Hideki Katabami ; Hiroshi Saito ; Tomohiro Yoneda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Tokyo, Japan
Conference Date: 26 September 2013
Page(s): 31 - 36
ISBN (Electronic): 978-0-7695-5086-2
DOI: 10.1109/MCSoC.2013.35
Regular:

In this paper, we propose a Globally-Asynchronous Locally-Synchronous Network-on-Chip (GALS-NoC) architecture for FPGAs. Each node in the proposed GALS-NoC is based on a soft-core processor... View More

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