IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock Gating Aware Low Power Global Reset ALU and Implementation on 28nm FPGA

2013 5th International Conference on Computational Intelligence and Communication Networks (CICN)

Author(s): Bishwajeet Pandey ; Jyotsana Yadav ; Jagdish Kumar ; Ravikant Kumar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Mathura, India
Conference Date: 27 September 2013
Page(s): 413 - 417
ISBN (Electronic): 978-0-7695-5069-5
DOI: 10.1109/CICN.2013.91
Regular:

In this paper, we apply clock gating technique in Global Reset ALU design on 28nm Artix7 FPGA to save dynamic and clock power both. This technique is simulated in Xilinx14.3 tool and implemented... View More

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