IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip

2013 16th Euromicro Conference on Digital System Design

Author(s): Ran Manevich ; Leon Polishuk ; Israel Cidon ; Avinoam Kolodny
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Los Alamitos, CA, USA
Conference Date: 4 September 2013
Page(s): 769 - 776
ISBN (Electronic): 978-1-4799-2978-8
DOI: 10.1109/DSD.2013.88
Regular:

Hierarchical topologies are frequently proposed for large Networks-on-Chip (NoCs). Hierarchical architectures utilize, at the upper levels, long links of the order of the die size. RC delays of... View More

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