IEEE - Institute of Electrical and Electronics Engineers, Inc. - Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder

2013 16th Euromicro Conference on Digital System Design

Author(s): G. Pastuszak ; M. Trochimiuk
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Los Alamitos, CA, USA
Conference Date: 4 September 2013
Page(s): 423 - 428
ISBN (Electronic): 978-1-4799-2978-8
DOI: 10.1109/DSD.2013.53
Regular:

This paper describes the architecture of the high-throughput interpolator used in motion estimation and compensation of the HEVC encoder. The architecture reads eight input samples and produces 64... View More

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