IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Efficient Hardware Implementation of a SAT Problem Solver on FPGA

2013 16th Euromicro Conference on Digital System Design

Author(s): Teodor Ivan ; El Mostapha Aboulhamid
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Los Alamitos, CA, USA
Conference Date: 4 September 2013
Page(s): 209 - 216
ISBN (Electronic): 978-1-4799-2978-8
DOI: 10.1109/DSD.2013.31
Regular:

A hardware analyzer for the Boolean satisfiability problem using a complete algorithm was developed for an Alter a DE2-70 Cyclone II FPGA board. In one clock cycle, all implications are computed,... View More

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