IEEE - Institute of Electrical and Electronics Engineers, Inc. - Logic emulation with forced assertions: A methodology for rapid functional verification and debug

2013 5th Asia Symposium on Quality Electronic Design (ASQED)

Author(s): Somnath Banerjee ; Tushar Gupta ; Sanjay Gupta
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2013
Conference Location: Penang, Malaysia
Conference Date: 26 August 2013
Page(s): 312 - 320
ISBN (CD): 978-1-4799-1312-1
ISBN (Electronic): 978-1-4799-1314-5
DOI: 10.1109/ASQED.2013.6643605
Regular:

To improve debugging turnaround time of complex System-on-chip (SoC) designs on FPGA based logic emulation systems, it is important to minimize the iterations through design recompilation or FPGA... View More

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