IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low-power circuit architecture for transistor electrical overstress (EOS) protection

2013 5th Asia Symposium on Quality Electronic Design (ASQED)

Author(s): Aw Chee Hong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2013
Conference Location: Penang, Malaysia
Conference Date: 26 August 2013
Page(s): 282 - 286
ISBN (CD): 978-1-4799-1312-1
ISBN (Electronic): 978-1-4799-1314-5
DOI: 10.1109/ASQED.2013.6643601
Regular:

As the transistor dimension keeps shrinking following trend predicted by Moore's Law, the voltage that transistor can sustain reliably is also reducing. For certain serial interface protocols... View More

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