IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimized clock gating cell for low power design in nanoscale CMOS technology

2013 5th Asia Symposium on Quality Electronic Design (ASQED)

Author(s): Aniryudh Reddy Durgam ; Ken Choi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2013
Conference Location: Penang, Malaysia
Conference Date: 26 August 2013
Page(s): 85 - 88
ISBN (CD): 978-1-4799-1312-1
ISBN (Electronic): 978-1-4799-1314-5
DOI: 10.1109/ASQED.2013.6643569
Regular:

This paper discusses a novel clock gating cell (CGC) optimized for high performance and low power design. The conventional CGC is analyzed along with other low power implementations of the CGC... View More

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