IEEE - Institute of Electrical and Electronics Engineers, Inc. - Improved test methodology for multi-clock domain SoC ATPG testing

2013 5th Asia Symposium on Quality Electronic Design (ASQED)

Author(s): Ee Mei Ooi ; Chin Hai Ang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2013
Conference Location: Penang, Malaysia
Conference Date: 26 August 2013
Page(s): 33 - 38
ISBN (CD): 978-1-4799-1312-1
ISBN (Electronic): 978-1-4799-1314-5
DOI: 10.1109/ASQED.2013.6643560
Regular:

This paper proposes a test strategy for improving SoC ATPG testing. On-chip clock controller (OCC) is used to yield better at-speed test coverage and pattern generation. In addition, clock gating... View More

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