IEEE - Institute of Electrical and Electronics Engineers, Inc. - A pipeline architecture with 1-cycle timing error correction for low voltage operations

2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)

Author(s): Insup Shin ; Jae-Joon Kim ; Yu-Shiang Lin ; Youngsoo Shin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2013
Conference Location: Beijing, China
Conference Date: 4 September 2013
Page(s): 199 - 204
ISBN (CD): 978-1-4799-1234-6
ISBN (Electronic): 978-1-4799-1235-3
DOI: 10.1109/ISLPED.2013.6629294
Regular:

We present a new timing error correction scheme which allows each pipeline stage to halt for one cycle only. The small timing penalty for the error correction operation in the proposed scheme... View More

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