IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

Author(s): A. Hori ; M. Segawa ; S. Kameyama ; M. Yasuhira
Sponsor(s): IEEE Electron Devices Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 1993
Volume: 40
Page Count: 7
Page(s): 1,675 - 1,681
ISSN (Paper): 0018-9383
ISSN (Online): 1557-9646
DOI: 10.1109/16.231578
Regular:

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi/sub 2/ film) as well as... View More

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