IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance

2011 Symposium on VLSI Circuits

Author(s): Kim, J.P. ; Taehyun Kim ; Wuyang Hao ; Rao, H.M. ; Kangho Lee ; Xiaochun Zhu ; Xia Li ; Wah Hsu ; Kang, S.H. ; Matt, N. ; Yu, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 15 June 2011
Page(s): 296 - 297
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-61284-175-5
ISSN (CD): 2158-5601
ISSN (Electronic): 2158-5636
ISSN (Paper): 2158-5601
Regular:

1Mb embedded STT-MRAM macro using 45nm CMOS process includes two key design features; a dual-voltage row decoder with a charge sharing scheme for read operations and a sensing circuit with two... View More

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