IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz f T BiCMOS process

2011 Symposium on VLSI Circuits

Author(s): Poulton, K. ; Jewett, B. ; Liu, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 15 June 2011
Page(s): 62 - 63
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-61284-175-5
ISSN (CD): 2158-5601
ISSN (Electronic): 2158-5636
ISSN (Paper): 2158-5601
Regular:

We describe a DAC which can operate at up to 7.2 GSa/s with 14-bit resolution or up to 12 GSa/s with 12-bit resolution. It uses a segmented architecture, with an R/2R ladder for the 10 LSBs;... View More

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