IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST

2011 Symposium on VLSI Circuits

Author(s): Fujiwara, H. ; Yabuuchi, M. ; Nakano, H. ; Kawai, H. ; Nii, K. ; Arimoto, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 15 June 2011
Page(s): 76 - 77
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-61284-175-5
ISSN (CD): 2158-5601
ISSN (Electronic): 2158-5636
ISSN (Paper): 2158-5601
Regular:

A chip-ID generating scheme with high-tamper resistance is proposed. This enables to extract a unique finger print from each chip by using random failure bits in an SRAM under the ID generation... View More

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