IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS

2011 Symposium on VLSI Circuits

Author(s): Proesel, J.E. ; Dickson, T.O.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2011
Conference Location: Kyoto, Japan, Japan
Conference Date: 15 June 2011
Page(s): 206 - 207
ISBN (CD): 978-4-86348-166-4
ISBN (Paper): 978-1-61284-175-5
ISSN (CD): 2158-5601
ISSN (Electronic): 2158-5636
ISSN (Paper): 2158-5601
Regular:

A power-efficient equalizing serial receiver, including a 2-stage continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE), is reported operating at data rates of up to... View More

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